? semiconductor components industries, llc, 2009 december, 2009 ? rev. 1 1 publication order number: nb7l585/d nb7l585 2.5v / 3.3v differential 2:1 mux input to 1:6 lvpecl clock/data fanout buffer / translator multi ? level inputs w/ internal termination description the nb7l585 is a dif ferential 1:6 lvpecl clock/data distribution chip featuring a 2:1 clock/data input multiplexer with an input select pin. the inx/inx inputs incorporate internal 50 termination resistors and will accept lvpecl, cml, or lvds logic levels. the nb7l585 produces six identical output copies of clock or data operating up to 5 ghz or 8 gb/s, respectively. as such, nb7l585 is ideal for sonet, gige, fiber channel, backplane and other clock/data distribution applications. the nb7l585 is powered with either 2.5 v or 3.3 v supply and is offered in a low profile 5mm x 5mm 32 ? pin qfn package. application notes, models, and support documentation are available at www.onsemi.com. the nb7l585 is a member of the gigacomm ? family of high performance clock products. features ? maximum input data rate > 8 gb/s ? data dependent jitter < 15 ps ? maximum input clock frequency > 5 ghz ? random clock jitter < 0.8 ps rms ? low skew 1:6 lvpecl outputs, 20 ps max ? 2:1 multi ? level mux inputs ? 175 ps typical propagation delay ? 55 ps typical rise and fall times ? differential lvpecl outputs, 800 mv peak ? to ? peak, typical ? operating range: v cc = 2.375 v to 3.6 v with gnd = 0 v ? internal 50 input termination resistors ? vrefac reference output ? qfn ? 32 package, 5mm x 5mm ? ? 40 o c to +85 o c ambient operating temperature ? these devices are pb ? free and are rohs compliant qfn32 mn suffix case 488am see detailed ordering and shipping information on page 8 of this data sheet. ordering information marking diagram http://onsemi.com 32 1 nb7l 585 awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package (note: microdot may be in either location) 50 50 in1 vt1 in1 50 50 in0 vt0 in0 figure 1. simplified block diagram 0 1 vrefac1 vrefac0 q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 q5 q5 v cc gnd + sel
nb7l585 http://onsemi.com 2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 910111213 16 15 14 32 31 30 29 28 25 26 27 in0 vt0 vrefac0 in0 in1 vt1 vrefac1 in1 gnd vcc q2 q3 vcc gnd q2 gnd vcc q5 q4 vcc q5 sel vcc q0 q1 vcc q0 exposed pad (ep) gnd q1 q3 q4 nc figure 2. pinout: qfn ? 32 (top view) nb7l585 table 1. input select function table sel* clk input selected 0 in0 1 in1 *defaults high when left open. table 2. pin description pin number pin name i/o pin description 1,4 5,8 in0, in0 in1, in1 lvpecl, cml, lvds input non ? inverted, inverted, differential data inputs internally biased to v cc /2 2,6 vt0, vt1 internal 100 center ? tapped termination pin for in0 / in0 and in1 / in1 31 sel lvttl/lvcmos input input select pin; low for in0 inputs, high for in1 inputs; defaults high when left open 10 nc ? no connect 11, 16, 18 23, 25, 30 v cc ? positive supply voltage. all v cc pins must be connected to the positive power supply for correct dc and ac operation. 29, 28 27, 26 22, 21 20, 19 15, 14 13, 12 q0, q0 q1, q1 q2,q2 q3, q3 q4, q4 q5, q5 lvpecl output non ? inverted, inverted differential outputs note 1. 9, 17, 24, 32 gnd negative supply voltage, connected to ground 3 7 vrefac0 vrefac1 ? output voltage reference for capacitor ? coupled inputs ? ep ? the exposed pad (ep) on the qfn ? 32 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be elec- trically and thermally connected to gnd on the pc board. 1. in the differential configuration when the input termination pins (vt0, vt1) are connected to a common termination voltage or left open, and if no signal is applied on inn/inn input, then the device will be susceptible to self ? oscillation. 2. all v cc and gnd pins must be externally connected to a power supply for proper operation.
nb7l585 http://onsemi.com 3 table 3. attributes characteristics value esd protection human body model machine model > 2 kv > 200 v r pu ? sel input pullup resistor 75 k moisture sensitivity (note 3) qfn ? 32 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 288 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v +4.0 v v io input/output voltage gnd = 0 v ? 0.5 to v cc +0.5 v v inpp differential input voltage |in ? in | 1.89 v i in input current through r t (50 resistor) 40 ma i out output current continuous surge 50 100 ma i vrefac vrefac sink or source current 1.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn32 qfn32 31 27 c/w jc thermal resistance (junction ? to ? case) (note 4) qfn32 12 c/w t sol wave solder 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb7l585 http://onsemi.com 4 table 5. dc characteristics positive lvpecl output v cc = 2.375 v to 3.6 v; gnd = 0 v; t a = ? 40 c to 85 c (note 5) symbol characteristic min typ max unit power supply v cc power supply voltage v cc = 3.3v v cc = 2.5v 3.0 2.375 3.3 2.5 3.6 2.625 v i cc power supply current (inputs and outputs open) 185 225 ma lvpecl outputs v oh output high voltage (note 6) v cc = 3.3 v v cc = 2.5 v v cc ? 1145 2155 1355 v cc ? 800 2500 1700 mv v ol output low voltage (note 6) v cc = 3.3 v v cc = 2.5 v v cc ? 2000 1300 500 v cc ? 1500 1800 1000 mv differential clock inputs driven single ? ended (note 7) (figures 5 & 6) v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v th input threshold reference voltage range (note 8) 1100 v cc ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 1200 mv vrefacx (for capacitor ? coupled inputs, only) v refac output reference voltage @100 a for capacitor ? coupled inputs, only v cc ? 1500 v cc ? 1200 v cc ? 1000 mv differential inputs driven differentially (figures 7 & 8) (note 9) v ihd differential input high voltage (in, in ) 1200 v cc mv v ild differential input low voltage (in , in ) gnd v ihd ? 100 mv v id differential input voltage (in , in ) (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration, note 10) (figure 9) 1050 v cc ? 50 mv i ih input high current in/in (vtin/vtin open) ? 150 150 a i il input low current in/in (vtin/vtin open) ? 150 150 a control input (sel pin) v ih input high voltage for control pin 2.0 v cc mv v il input low voltage for control pin gnd 0.8 mv i ih input high current ? 150 150 a i il input low current ? 150 150 a termination resistors r tin internal input termination resistor (measured from inx to vtx) 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. lvpecl outputs (qn/qn ) loaded with 50 to v cc ? 2 v for proper operation. 7. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 8. v th is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb7l585 http://onsemi.com 5 table 6. ac characteristics v cc = 2.375 v to 3.6 v; gnd = 0 v; t a = ? 40 c to 85 c (note 11) symbol characteristic min typ max unit f max maximum input clock frequency; v outpp 400 mv 5 7 ghz f datamax maximum operating data rate (prbs23) 8 10 gbps f sel maximum toggle frequency, sel 1.0 1.5 ghz v outpp output voltage amplitude (@ v inppmin ) f in 4 ghz (note 12) (figures 8 and 10) f in 5 ghz 550 400 800 650 mv t plh , t phl propagation delay to differential outputs, @ 1 ghz, measured at differential crosspoint in/in to q/q sel to q 125 75 175 200 250 300 ps t plh tc propagation delay temperature coefficient 50 f s/ c tskew output ? output skew (within device) (note 13) device ? device skew (tpd max ? tpdmin) 20 100 ps t dc output clock duty cycle (reference duty cycle = 50%) f in 5.0 ghz 45 50 55 % n phase noise, f in = 1 ghz 10 khz 100 khz 1 mhz 10 mhz 20 mhz 40 mhz ? 135 ? 137 ? 149 ? 150 ? 150 ? 151 dbc t n integrated phase jitter (figure x) fin = 1 ghz, 12 khz 20 mhz offset (rms) 36 fs t jitter rj ? output random jitter (note 14) f in 5.0 ghz dj ? residual output deterministic jitter (note 15) 8 gbps 0.2 5 0.8 15 ps rms ps pk ? pk crosstalk induced jitter (adjacent channel) (note 17) 0.7 psrms v inpp input voltage swing (differential configuration) (note 16) 100 1200 mv t r, , t f output rise/fall times @ 1 ghz (20% ? 80%), q, q 25 55 85 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured using a 400 mv pk ? pk source, 50% duty cycle clock source. all output loading with external 50 to v cc ? 2 v. input edge rates 40 ps (20% ? 80%). 12. output voltage swing is a single ? ended measurement operating in differential mode. 13. skew is measured between outputs under identical transitions and conditions. duty cycle skew is defined only for dif ferential operation when the delays are measured from cross ? point of the inputs to the crosspoint of the outputs. 14. additive rms jitter with 50% duty cycle clock signal. 15. additive peak ? to ? peak data dependent jitter with input nrz data at prbs23. 16. input voltage swing is a single ? ended measurement operating in differential mode. 17. crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. f in , clock input frequency (ghz) figure 3. clock output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typical) output voltage amplitude (mv) 0 200 1000 01 8 7 6 5 4 23 q amp (mv) 800 600 400
nb7l585 http://onsemi.com 6 figure 4. input structure figure 5. differential input driven single ? ended figure 6. v th diagram figure 7. differential inputs driven differentially figure 8. differential inputs driven differentially figure 9. vcmr diagram figure 10. ac reference measurement v ihd v ild v id = |v ihd(in) ? v ild(in) | in in in v th in in in in in q q t plh t phl v inpp = v ih (in) ? v il (in) v outpp = v oh (q) ? v ol (q) 50 50 inx vtx inx v cc v ee v thmin v thmax v th in v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v ee v cmrmin v cmrmax v cmr in in v ihdmax v ildmax v id = v ihd ? v ild v ihdtyp v ildtyp v ihdmin v ildmin v th v ih v il figure 11. sel to qx timing diagram tpd tpd v cc / 2 v cc / 2 sel qx qx
nb7l585 http://onsemi.com 7 v cc lvpecl driver in 50 z o = 50 z o = 50 50 in nb7l585 v cc v cc cml driver in 50 z o = 50 z o = 50 50 in v cc v t = v cc figure 12. lvpecl interface figure 13. lvds interface v t = v cc ? 2.0 v figure 14. standard 50 load cml interface v cc lvds driver in 50 z o = 50 z o = 50 50 in v cc v t = open gnd gnd gnd gnd gnd gnd v cc differential driver in 50 z o = 50 z o = 50 50 in v cc v t = vrefac* figure 15. capacitor ? coupled differential interface (v t connected to v refac ) gnd gnd *vrefac bypassed to ground with a 0.01 f capacitor. clkx clkx nb7l585 nb7l585 nb7l585 figure 16. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v
nb7l585 http://onsemi.com 8 device ordering information device package shipping ? nb7l585mng qfn ? 32 (pb ? free) 74 units / rail NB7L585MNR4G qfn ? 32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb7l585 http://onsemi.com 9 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb7l585/d gigacomm is a trademark of semiconductor component industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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